SDRAM without HPS

waitrequest is a required signal with Avalon. When it is high, control signals must be held until 1 cycle after waitrequest goes low. It's not random. It's based on what's happening in the system interconnect at any time. See the Avalon spec here: https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/introduction-to-the-interface-specifications.html