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Honored Contributor
Honored ContributorSDRAM setup violation when reading
Hi, I am using a Cyclone 4 FPGA running at 100Mhz. My design has a SDRAM interface also running at 100Mhz. Currently the PLL is generating 1 clock, which is used to clock the SDRAM...
Altera_ForumHonored Contributor
Honored ContributorThanks for your fast reply!
note that a lot of that 2.9ns clock delay(which i assume is the path for the clock to get off chip so it can be sent to the sdram), should cancel out with the data required path, whose latch clock goes through a similar delayThis is only valid when writing. Or am I missing something? When reading, the memory spec. gives a 6ns access time. I don't have a lot of margin... As I don't want to modify the SDRAM controller, I will go for a second clock with another phase. Does it make sense to use an ALTDDIO buffer ?
