SDRAM setup violation when reading

Are you sure the analysis is correct? Note that a lot of that 2.9ns clock delay(which I assume is the path for the clock to get off chip so it can be sent to the sdram), should cancel out with the Data Required Path, whose latch clock goes through a similar delay(it doesn't go through an output buffer). Attach the timing report if you want, but be sure to do "report_timing -setup -npaths 1 -detail full_path ..."

6ns is the external round-trip delay, correct? That's what is really chewing up a lot of you margin.

Using another phase of the clock to transmit or receive should work. Another option is to clock data in on the falling edge, and then add a multicycle to tell timeQuest you're shooting for the next edge:

set_multicycle_path -setup -from [get_ports {sdram_data_in[*]}] 2

That should make the setup relationship 15ns on these paths and the hold relationship 5ns. If your external -min delay is relatively large, say 3ns, then meeting that min requirement should be pretty easy.