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From the you attached for the sdram controller in DE0 Nano, I can see that you instantiated ADC (analog digital converter) in the top level entity, however I could not find the vhdl file for ADC processing, do you mind to send me the ADC file?
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Look at the top-level code again - there is no ADC component instantiated.
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I tried to understand how to create Qsys custom component for ADC Controller from Altera document (Using DE0 Nano ADC COntroller), too bad that those files are written in Verilog and I have difficulty to apply to my VHDL system, I also have sent a service request to Altera team but they do not have vhdl files for this, appreciate your help,
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I have not used the ADC on the DE0-nano. Its an SPI device, so its pretty easy to write a controller from scratch.
The type of controller you write depends on what you want to do with it, for example,
1. Use an existing "SPI Master Controller" and write software to interface to the ADC.
2. Create an Avalon-MM slave with 8 addresses, and when you access any one of these 8 addresses perform a conversion. Use a DMA controller to transfer blocks of samples to SDRAM.
3. Create an Avalon-MM ADC controller interface, where you set the ADC clock frequency, and the rate at which it auto-reads channels. Software then just reads the last conversion value from 8 registers.
Cheers,
Dave
Honored Contributor
