SDRAM on DE0-nano board

Hi Dave,

From the you attached for the sdram controller in DE0 Nano, I can see that you instantiated ADC (analog digital converter) in the top level entity, however I could not find the vhdl file for ADC processing, do you mind to send me the ADC file?

I tried to understand how to create Qsys custom component for ADC Controller from Altera document (Using DE0 Nano ADC COntroller), too bad that those files are written in Verilog and I have difficulty to apply to my VHDL system, I also have sent a service request to Altera team but they do not have vhdl files for this, appreciate your help,

Thank you