Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

SDRAM on DE0-nano board

Hi, I am still not having any success writing and reading from the SDRAM on on the DE0-nano board from the FPGA. I have built a system in qsys which includes a Nios II and SDRAM controller an...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

--- Quote Start ---

I have checked over and over again the pin assignments and qsys settings ...

--- Quote End ---

The .qar file you sent generates warning messages about unconstrained clocks and paths and TimeQuest fails, so I think that is the root of your problem. Create an .SDC file for your project based on the example I provided.

This experience should help you understand that an HDL design consists of (at least);

1. The HDL design files.

2. The device constraints file (device type + pin assignments)

3. The timing constraints file (the .SDC file)

Cheers,

Dave