Honored Contributor
Honored ContributorDear Daixiwen,
thank you very much for your detailed reply. --- Quote Start --- Using at the same time numeric_std and the non standard std_logic_arith and std_logic_unsigned is known to cause some problems. You should remove std_logic_arith and std_logic_unsigned, and use the signed and unsigned types provided by numeric_std to do all your arithmetic operations. --- Quote End --- I will try to modify the code in that way to get rid of these 'arithmetic' collisions. --- Quote Start --- Then you don't seem to have anything connected to your full and empty ports. --- Quote End --- Yes, that's true. I didn't think that I have to monitor these signals as I count all words going in and out. Do you think that this is not enough? --- Quote Start --- What clock domain is the base_address vector comming from? If it is clk_rd then you can't use it directly in your process, that is clocked on the clk domain. You need proper synchronization. Any resource on the net abouk clock domain crossing in VHDL should help you find out how. --- Quote End --- No no, the base_address is a kind of constant, which points at the beginning of the image data in the ram. It's just a static address offset and has no dedicated clk. --- Quote Start --- Another problem could come from the fitter and TimeQuest. By default it will consider both clocks from being in the same domain, and if you have any signal crossing between the two domains it will determine the timing appropriately. If the two clocks are synchronous then this isn't really a problem and it can work. But if they are completely asynchronous this task is impossible and the final design won't meet timing requirements. You need to declare the two clocks in different groups in Timequest so that it doesn't try to optimize the timing between the two of them. You also need to be sure that any signal going from one domain to the other is properly synchronized. It is already done for the data path because you are using a dual clock FIFO, but check any other control signal that crosses the boundary. --- Quote End --- To my shame I have to admit that I've not used timequest up to now, because I don't know how to configure it. I thought that the most critial points would be done by the altera megafunction fifo, which is capable of handling asynchronous clocks. Regarding the maximum operation clock, I've always hoped that 100Mhz are far enough away from the Cyclone IV capabilities. I do definitely know that the timing 'performance' of a project is a very basic and important point and I intend to learn TimeQuest!! I'm quite skilled in programming microcontrollers, but the parallel architecture of a fpga is often not very easy!! Again, thank you very much for you valuable tips! I will try to take everything you said into consideration! Kind regards!:)
