SDRAM Framebuffer with two asynchronous clocks

First a general comment:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

Using at the same time numeric_std and the non standard std_logic_arith and std_logic_unsigned is known to cause some problems. You should remove std_logic_arith and std_logic_unsigned, and use the signed and unsigned types provided by numeric_std to do all your arithmetic operations.

Then you don't seem to have anything connected to your full and empty ports.

What clock domain is the base_address vector comming from? If it is clk_rd then you can't use it directly in your process, that is clocked on the clk domain. You need proper synchronization. Any resource on the net abouk clock domain crossing in VHDL should help you find out how.

Another problem could come from the fitter and TimeQuest. By default it will consider both clocks from being in the same domain, and if you have any signal crossing between the two domains it will determine the timing appropriately. If the two clocks are synchronous then this isn't really a problem and it can work. But if they are completely asynchronous this task is impossible and the final design won't meet timing requirements. You need to declare the two clocks in different groups in Timequest so that it doesn't try to optimize the timing between the two of them. You also need to be sure that any signal going from one domain to the other is properly synchronized. It is already done for the data path because you are using a dual clock FIFO, but check any other control signal that crosses the boundary.