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New Contributor

2 years ago

SDRAM Controller Intel FPGA IP not working as expected

Hello! I'm writing a simple RAM and VGA testing module. At first data gets written to the SDRAM (repeatedly 0 to 4095) and then it's read from the sdram and written to a FIFO to show it as p...

Generic Io

merchant-

New Contributor

2 years ago

I have had some similar issues, my timing and waveforms are all correct though nothing is returned when after a read cycle (even when read valid is high). On a forum I saw that the Avalon-MM interface could have a minimum burst transfer for the IP core though the official documentation does not say any of this and is not great.

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SDRAM Controller Intel FPGA IP not working as expected

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