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TimSch's avatar
TimSch
Icon for New Contributor rankNew Contributor
2 years ago

SDRAM Controller Intel FPGA IP not working as expected

Hello! I'm writing a simple RAM and VGA testing module. At first data gets written to the SDRAM (repeatedly 0 to 4095) and then it's read from the sdram and written to a FIFO to show it as p...
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AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi Tim,


I think there is a Manual that you can refer to run the test. It's should explain the purpose of LED and behavior of the SDRAM.


I think the readvalid signal will go high after the read signal is go high. It's will indicate the data is valid and available .



Regards,

Adzim


TimSch's avatar
TimSch
Icon for New Contributor rankNew Contributor
2 years ago

Hello Adzim,

that's true! The problem is that the readvalid signal should go down if the next value isn't ready yet and that doesn't seem to happen.

Although I found another solution using a completely different controller, I would be interested in the cause of the issue.

The settings of the IP are so simple, I would consider it as foolproof. If there is any chance that this is not an issue caused by me but some "bug" in the IP it may be interesting to investigate it.