Forum Discussion

New Contributor

2 years ago

SDRAM Controller Intel FPGA IP not working as expected

Hello! I'm writing a simple RAM and VGA testing module. At first data gets written to the SDRAM (repeatedly 0 to 4095) and then it's read from the sdram and written to a FIFO to show it as p...

Generic Io

AdzimZM_Altera

Regular Contributor

2 years ago

Hi Tim,

I'm not really familiar with this application.

Usually I will always checking the timing parameter in the IP.

Does the example design working normally to verify the SDRAM is working?

Regards,

Adzim

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SDRAM Controller Intel FPGA IP not working as expected

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