Forum Discussion
TimSch
New Contributor
New ContributorSDRAM Controller Intel FPGA IP not working as expected
Hello! I'm writing a simple RAM and VGA testing module. At first data gets written to the SDRAM (repeatedly 0 to 4095) and then it's read from the sdram and written to a FIFO to show it as p...
AdzimZM_Altera
Regular Contributor
Regular ContributorHi Tim,
I'm not really familiar with this application.
Usually I will always checking the timing parameter in the IP.
Does the example design working normally to verify the SDRAM is working?
Regards,
Adzim
