sdram bank interleave storage

Hi ,

SDRAM usually split to 4 banks, in each bank mem also split to several kilo rows(or pages), you can read details of address bus from datasheet.

When visit different pages in the same bank, controller will de-active current page and then active the next page for visit. This operation need 10~20 cycles to complete.

If data stored in different bank, we can keep 4 pages active in 4 banks. Swtich form one bank to another bank seems faster than switch between pages in the same bank.

So the key is how you allocate data to the SDRAM.

By the way, use large "burst length" value will greatly increase the efficieny you expected.