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Altera_Forum
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14 years ago

SDR to DDR timing constraint conversion

Hi, My design uses classic timing analyser and I have the following constraints for a SDR source synchronous interface. tsu_requirement/th_requirement for input and tco_requirement/min_t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

In general, the problems with Tsu/Th/Tco, like the fact that they basically ignore the difference between rising/falling edges, works in the favor of DDR interfaces, and actually makes it easy. Just use what you have, knowing it will apply to both edges, and you should be all right.