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Altera_Forum
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14 years ago

SDR SDRAM controller problem

Hi, I have developed my own SDR SDRAM controller in VHDL to integrate it with the rest of a design inside a Cyclone IV for image processing. By testing the controller I write in the SDRAM 307...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Hi John,

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The FPGA device is EP4CE22E22C7 and supports OCT but it didn't work with the OCT resistance.

Only when I reduce the slew rate to the slowest it works better but not as good as when I use the capacitor.

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Thanks for the feedback.

If you're involved with the design of a new board, its always a good idea to place an external source termination on any point-to-point clock-like signal. If you have a clock-like signal going multiple places, then you can use dual-source terminations, or add buffers, and source terminate the buffers.

Ringing clock edges can ruin your day :)

Cheers,

Dave