SDR SDRAM controller problem

Hi John,

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Problem solved

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Great!

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The second issue was concerning the clock signal I lead to the SDRAM. It seems it had ringing or some kind of a noise by causing malfunction to the communication between controller and SDRAM. By placing a small capacitor (15pF) between the clock line and the GND signal all errors disappeared. As you realize hardware is custom too.

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Depending on the FPGA, some devices have the option to enable a series resistor on outputs. Check the handbook for your device, or just try enabling a series termination and see if Quartus allows it.

Using a series termination will result in a cleaner clock, since it will have faster edge-rates (ideally) without ringing. Using a capacitor is simply slowing down the edge-rates (its an RC filter, where the R is the output impedance of the driver).

Cheers,

Dave