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In the design so far I used to launch data on a falling edge and SDRAM or other peripherals latch them on rising edge. In such a way I believed that the design will meet timing requirements since there is not high frequency. Even if I have not constrain the design shouldn't be working?
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What makes you think using the falling-edge will help? That only makes sense if you know what the clock-to-output delay of the FPGA is, and the setup and hold requirement of the SDR is, and then determine that you would have excessive setup time and minimal hold time using the rising-edge, so then you use the falling-edge to trade-off setup time for increased hold time. However, that type of analysis is not possible on an FPGA without applying timing constraints. FPGAs have programmable delays in their I/O elements that are used adjust timing.
But, sure, it might be possible to meet timing without constraints. Have you looked at the external signals with an oscilloscope? Perhaps your timing is ok, but you have ringing on your signals that are corrupting the data.
Cheers,
Dave
Honored Contributor
