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Altera_Forum
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13 years ago

SDR SDRAM controller problem

Hi, I have developed my own SDR SDRAM controller in VHDL to integrate it with the rest of a design inside a Cyclone IV for image processing. By testing the controller I write in the SDRAM 307...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thanks again for your answer.

I will study the links you provided and also Altera's documents.

I am convinced about constraining the design and I am working on that but I still have a question.

In the design so far I used to launch data on a falling edge and SDRAM or other peripherals latch them on rising edge. In such a way I believed that the design will meet timing requirements since there is not high frequency. Even if I have not constrain the design shouldn't be working?

Regards,

John