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Altera_Forum
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14 years ago

SDR SDRAM controller problem

Hi, I have developed my own SDR SDRAM controller in VHDL to integrate it with the rest of a design inside a Cyclone IV for image processing. By testing the controller I write in the SDRAM 307...
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Altera_Forum
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14 years ago

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Since all you are telling me that I need to constrain my design I will follow that. I thought I do not need to do it if frequency is low but probably I am wrong.

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Yes, you are wrong :)

You have to have timing constraints on the clock(s) and the I/Os, so that the synthesis tool can make placement decisions related to the internal routing delays, and so that it can program the delay lines in the I/O elements (these delay lines are used to meet external setup and hold time requirements).

Rysc has a tutorial on the Altera Wiki

http://www.alterawiki.com/wiki/timequest

and this thread has a document I wrote when asking Rysc some questions:

http://www.alteraforum.com/forum/showthread.php?t=31457

Cheers,

Dave