SDR SDRAM controller problem

Thank you all for your answers.

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You can make your timing requirements easier to meet by using a lower clock frequency to the SDR. However, you still need to meet refresh timing requirements.

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First I had applied SDRAM clock at 50MHz but the design did not work even when I reduced the frequency at 12.5MHz.

Refresh behaviour has been provised but I am not sure if it is working properly since even if I remove it same problems occur.

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You will also need to constrain the timing so your design will synthesize properly. If you do not constrain your design, it will most likely not function properly.

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FPGA timing; you must make sure all sdram signals generated by fgpa mantain a good synchronization across routing and i/o pins, namely they have no excessive skew or trasmission delays. For this part, you need to carefully constrain your design.

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Since all you are telling me that I need to constrain my design I will follow that. I thought I do not need to do it if frequency is low but probably I am wrong.

Regards,

John