SDR SDRAM controller problem

Hi John,

Let's say your design must comply with two sets of timing requirements:

- SDRAM timing specification itself, namely row precharge time, data latency, refresh period, and so on. This is sort of 'functional' timing and depends uniquely on your hdl code.

- FPGA timing; you must make sure all sdram signals generated by fgpa mantain a good synchronization across routing and i/o pins, namely they have no excessive skew or trasmission delays. For this part, you need to carefully constrain your design.