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Altera_Forum
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14 years ago

SDR SDRAM controller problem

Hi, I have developed my own SDR SDRAM controller in VHDL to integrate it with the rest of a design inside a Cyclone IV for image processing. By testing the controller I write in the SDRAM 307...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Noting that you have written your own SDRAM controller, have you included refresh behavior? If not, it would be best to go back and re-read the SDRAM datasheet.

You will also need to constrain the timing so your design will synthesize properly. If you do not constrain your design, it will most likely not function properly.