schematic block to verilog (behavioral model) conversion....possible?

Hi all,

My current project is a MAX CPLD codes in schematic blocks (all AND, NOT, OR, DFF, etc logics). It works fine so far, however due to more and more user requirements, it is not possible possible to continue as the state diagram getting more and more complicated.

I tried the Quartus conversion tools, however the converted verilog code I get is all structural format and there is even more confuse if I continue work on it.

Is there a painless way to convert the schematic to a more 'understandable' verilog behavioral model code?

I was thinking writing the new sub-module in verilog, wrap it as schematic block, and place it into the existing top module (which is in schematic form). But again my top module needs a hell-lot changes too!