Scaling core clock of 100MHz to 23MHz & 20MHz

It's not part of the MegaCore, it's a user design. If I remember right, there have been also Altera design examples with DPA, but I don't remember where I had seen them.

It's not particularly necessary to enable rx_outclock, but I wonder which clock you are using to process your received data.

I give you my code as is. It's for a 4x4 multichannel

LVDS revceiver. As an additional hint, the dpa_reset[1:4] signal

is used as start trigger for train sequence, it is generated

by another design component communicating with LVDS

sender.

4'h3 is the respective train pattern.

 always @ (posedge RESET or posedge rx_outclock_sig)
 begin
  if (RESET)
  begin
   train_timer <= 8'hff;
   train <= 0;
   rx_dpa_locked_v <= 0;
   ModulFehler <= 4'hf;
  end
  else
  begin
   if (dpa_reset)
   begin
    train_timer <= 0;
    train <= dpa_reset;
    rx_dpa_locked_v <= 0;
   end
   else
   begin
    case (train_timer)
     255:
      begin
       train <= 0;
       rx_channel_data_align_sig <= 0;
       for (N=1;N<=4;N=N+1)
        if (train)
        begin
         ModulFehler = 0;
         for (M=8*N-8;M<8*N;M=M+1)
          if (!rx_dpa_locked_sig || rx_cda_max_sig)
          begin
           ModulFehler = 1;
          end
        end
      end
     default:
      begin
       for (N=1;N<=4;N=N+1)
        for (M=8*N-8;M<8*N;M=M+1)
           if (train)
         begin
          if ((train_timer % 8) == 7 && rx_dpa_locked_sig)
           rx_dpa_locked_v <= 1;
          if ((train_timer % 8) == 7 && rx_dpa_locked_v &&
           !rx_cda_max_sig &&
           {rx_out_sig_i,rx_out_sig_i,
           rx_out_sig_i,rx_out_sig_i} != 4'h3)
           rx_channel_data_align_sig <= 1;
          else
           rx_channel_data_align_sig <= 0;
         end
       train_timer <= train_timer + 1;
      end
    endcase
   end
  end
  for (N=1;N<=4;N=N+1)
   for (M=8*N-8;M<8*N;M=M+1)
   begin
    rx_cda_reset_sig = dpa_reset;
    rx_reset_sig = dpa_reset;
    rx_dpll_hold_sig = !train;
   end
 end