SC_FIFO generation under SOPC

Hi,

i've just generated a design under SOPC Builder using single clock fifo (sc_fifo).

i've seen that sc_fifo code source takes place at X:/altera/81/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v (verilog source).

setup_sim.do infers sc_fifo.vhd source which calls a component named altera_avalon_sc_fifo which is not compiled by default because it is a verilog source. No vhdl sources for altera_avalon_sc_fifo exist.

Fortunately, there is a file named sc_fifo.vho in root design directory which has been generated during sopc builder process.

And when i compile it, it works fine.

Is it a bug during setup_sim generation ? or is it normal to proceed some adaptations in setup_sim.do file ?