Forum Discussion
GDeXi
Occasional Contributor
6 years agoThanks for you apply.
I did some test like LED linking, and find it also failed with same error code .
by the way , the FPGA configuration clock source is external 125MHZ and generate 125Mhz to load image . is this should be check ?
ShafiqY_Intel
Frequent Contributor
6 years agoHi GDeXi,
Have you tried to reduce clock source to 50MHz? Is it you get the similar error?
Plus, when you program .jic file into Stratix 10, what is your TCK frequency used?
Can you kindly try to reduce your TCK frequency to 6 MHz ?
Below link is the command to change TCK frequency (on page 14= 2.8. Changing the TCK Frequency)
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_usb_blstr_ii_cable.pdf#page=14
Thanks