Altera_Forum
Honored Contributor
16 years agoRX'ing different data rates with ALTGX using reverse serial loopback
I am trying to instantiate 16 ALTGX transceivers in a Stratix IV GX (1517-pin) package.
I want all of the channels to operate in reverse serial loopback mode - I am never transmitting data from user logic, it is always being looped-back from the RX path. I want each channel to independently operate at 8.5, 4.25, 2.125 and 1.0625 Gbps, in Basic mode. I realize that if I were transmitting my own data I would need to use dynamic reconfiguration to change the CMU/local divider settings. However, since I am always using reverse serial loopback (pre-CDR), do I need to concern myself with dynamic reconfiguration and multiple MIFs for each data rate? If I set my CDR-locking to Lock To Data (and never to Lock to Reference), should I have to worry about the RX-path's data rate? Won't the recovered clock be representing the appropriate data rate regardless of the cruclk/pll_input?