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Altera_Forum
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16 years ago

RX'ing different data rates with ALTGX using reverse serial loopback

I am trying to instantiate 16 ALTGX transceivers in a Stratix IV GX (1517-pin) package.

I want all of the channels to operate in reverse serial loopback mode - I am never transmitting data from user logic, it is always being looped-back from the RX path.

I want each channel to independently operate at 8.5, 4.25, 2.125 and 1.0625 Gbps, in Basic mode.

I realize that if I were transmitting my own data I would need to use dynamic reconfiguration to change the CMU/local divider settings. However, since I am always using reverse serial loopback (pre-CDR), do I need to concern myself with dynamic reconfiguration and multiple MIFs for each data rate?

If I set my CDR-locking to Lock To Data (and never to Lock to Reference), should I have to worry about the RX-path's data rate? Won't the recovered clock be representing the appropriate data rate regardless of the cruclk/pll_input?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    If frequency A=2B=4C, you can reconfig you transceiver without reconfiging the pll in transceiver; if A=8D, i'm not sure if the pll support the 4x mode.

    But if the different frequencies do not have double relations, you must reconfig both the pll and the transceiver.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Can the CDR lock to data if even if the data rate selected/set on the General page of the MegaWizard doesn't match the rate of received data?

    In the MegaWizard is it possible to set the data rate to frequency A, and then successfully receive data at other frequencies A, B, C, and D?

    If I set A to 8.5 Gbps, can I receive (and lock to) data rates of 1.0625, 2.125, 4.25 and 8.5 Gbps? Or do I need to dynamically reconfigure the transceiver to the different data rates?
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    In ALTGX transceiver, a pll is used for receiver. When transceiver is set as Lock To Data mode, the pll will lock to the CDR clock. But the pll's working frequency is limited. It can't work at all frequency when transceiver is set at one speed.