Running NIOS code from SSRAM

Hi Jake and others,

Thanks for the information.

1. I calculated the data delay from the NIOS entity port to the SRAM data bus pins and the delay from the PLL port to SRAM Clock pin in the FPGA using the below two commands.

# # Reports path delay on all the data lines.
report_path -from |q}] -to }] -npaths 40 -panel_name "SRAM_OUT_DATA_DELAY"
# ## report clock delay
report_path -from }] -to  -npaths 40 -panel_name "Report Path"

The average data delay is 6.188188ns and the clock delay is 4.24 ns. In this case the clock delay is less than the data delay. So, should the phase shift of the SRAM clock should be 6.188188-4.24 = 1.948188 or should it be -1.948188.

2. I calculated the delay of the data from the data pin to the first register in the NIOS using the command shown below:

report_path -from }] -to |d}] -npaths 40 -panel_name "SRAM_IN_Data_Delay"

Using the result of the above report path command, I got a average input data delay of 0.657063. Should I consider this delay in the phase of the clock to the SRAM?

Thanks,

Kumaran