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Altera_Forum
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16 years ago

Running NIOS code from SSRAM

Hi, I am trying to run a NIOS code from CY7C1354CV25 SSRAM(32 bits data line) and it is very unstable. My hardware is sharing the address and data bus with a flash device PC48F4400P0TB0E (16 bits ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

1 - Basically the idea is to get the clock to the SRAM center aligned with all of the data and control signals. So in my particular case, I was running the SRAM at 100MHz. After calculating delays and everything I decided that I wanted the clock going to the SRAM to be -4.8ns shifted from my regular clock. This translated to the -172.8 degree shift you see in the constraint.

2 - Let me take some time to go back and see how I got to my setup and hold values and I'll get back to you.

3 - You can most certainly constrain it as I have done.

4 - cy7c1380D

Have you seen this free training on constraining source-synchronous interfaces?

http://www.altera.com/education/training/courses/odsw1160

Jake