Running NIOS code from SSRAM

Hi Jake,

Thanks for the code and quick response.

1. I have the SRAM clock connected to a separate port in the PLL as you have mentioned, but I do not know how to determine the phase shift. How did you calculate the phase for sram_clk_int clock?

2. Also for the set_output_delay calculation, I used the formula shown below(it ignore the board delay):

set_output_delay -clock<clock source> -min -Th [get ports *]

The difference I see between your SDC and mine is the minimum set_output_delay has negative value in mine. Am I missing something?

3. Do we need to use virtual clock for constraining the SRAM pins or can I do the constraint like what you have done?

4. Do you know the part number of the SRAM and flash on your design, so that I can try to decode what exactly you are doing.

Thanks

Kumaran