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Altera_Forum's avatar
Altera_Forum
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15 years ago

running C without jtag

Hello,

I'm working on a module that is a part of a big project that's done on several stratix 3 FPGAs on a Gidel board. My problem is this:

In all the NIOS guides that I read I only see that the C code is being run/started from a GUI (NIOS IDE) which is activated via jtag/USB blaster or something like that. could someone refer me to a guide/reference that explains how to choose a C program and have it connected to the SOPC designer (or something like that) so that when I load the bitstream to the FPGA the code is already there.

Maybe I'm not explaining myself too well. What I mean is that the program will not need a jtag so that when the FPGA is loaded it will always work and only when some bit in the RTL is triggered it will start a method of the code.

Thanks,

Ayal

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Ayal,

    There are any number of ways that this can be done. The simplest is probably just to point your Reset Address at a non-volatile memory (CFI flash or EPCS), program the flash, and then allow the processor to load the code from this non-volatile memory on boot/reset.

    There are other methods mentioned in the Advanced Boot Copier AN (an-458 (http://http://www.altera.com/literature/an/an458.pdf)). It sounds like you'd be interested in this document.

    Cheers,

    - slacker