Honored Contributor
Honored ContributorHi,
just my two cents... You have a mix-up of variable assignment (cont := cont+1) which takes place immediately and signal assignments " <= " which take place "once" the condition is met. Additionally you should synchronize the process for concatenating the command to sysclk rather using the outputflag of the UART process for stringent clock synchronous design... Additionally the cont variable increases to 4 (being pure combinatorical, not registered) with the RxReady being '1', not with the rising edge of RxReady indicating a new command being received. It may already solve the issue, if you define cont as a signal as well and rewrite the condition from "If RxReady = '1' " to "If Rising_Edge(RxReady)" to envoke these code lines only once for each time you get a new byte by the UART... Regards, Carlhermann
