RRC Matched Filter Design

great you have reached the receiver now.

The receiver rrc filter has to be same as transmitter. Though the number of taps, sampling rate or any interpolation/decimation may be different from that of Tx filter.

The idea is both filtering of noise as well as doing correlation to maximise snr.

The correlation part requires reversal of coefficients in principle. But as long as the filter is symmetrical then you are free to reverse it and see what you get !!

since I haven't heard of anyone designing asymmetric rrc coeffs I better not swear at those unpractical dsp writers who also keep talking about infinity and minus infinity things.

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great you have reached the receiver now.

The receiver rrc filter has to be same as transmitter. Though the number of taps, sampling rate or any interpolation/decimation may be different from that of Tx filter.

The idea is both filtering of noise as well as doing correlation to maximise snr.

The correlation part requires reversal of coefficients in principle. But as long as the filter is symmetrical then you are free to reverse it and see what you get !!

since I haven't heard of anyone designing asymmetric rrc coeffs I better not swear at those unpractical dsp writers who also keep talking about infinity and minus infinity things.

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Actually, I implemented the RRC at the receiver and simulated in ModelSim. First, I thought I need to decimate by 8 in addition to filtering (I upsampled by 8 in the transmitter, if you remember) but I realized that this is gonna distort the signal since it will come out as 1 sample per symbol! I filtered without decimation. The signal looked exactly the same, like no filtering happened. Here where I thought the mathematical definition might mean something else.

I followed your advice and modeled the demodulator in MATLAB, but I got the same result... like no filtering happened. After a while, I started to put all what I read together... I need to add noise! Indeed, I added noise in MATLAB and observed the signal... this time, filtered like no noise happened! :D

PS: No need to swear at those unpractical dsp writers :D Writers whom I read for were practical I believe:

[1] Louis Litwin, "Matched filtering and timing recovery in digital receivers", rfdesign.com, September 2001

[2] Eric Jacobsen, http://www.dsprelated.com/showarticle/60.php

These were really useful.

Thank you for assisting me during this project KAZ :) Now I'm moving to carrier and symbol recovery, wish me luck.

Cheers

--- Quote Start ---

great you have reached the receiver now.

The receiver rrc filter has to be same as transmitter. Though the number of taps, sampling rate or any interpolation/decimation may be different from that of Tx filter.

The idea is both filtering of noise as well as doing correlation to maximise snr.

The correlation part requires reversal of coefficients in principle. But as long as the filter is symmetrical then you are free to reverse it and see what you get !!

since I haven't heard of anyone designing asymmetric rrc coeffs I better not swear at those unpractical dsp writers who also keep talking about infinity and minus infinity things.

--- Quote End ---

Actually, I implemented the RRC at the receiver and simulated in ModelSim. First, I thought I need to decimate by 8 in addition to filtering (I upsampled by 8 in the transmitter, if you remember) but I realized that this is gonna distort the signal since it will come out as 1 sample per symbol! I filtered without decimation. The signal looked exactly the same, like no filtering happened. Here where I thought the mathematical definition might mean something else.

I followed your advice and modeled the demodulator in MATLAB, but I got the same result... like no filtering happened. After a while, I started to put all what I read together... I need to add noise! Indeed, I added noise in MATLAB and observed the signal... this time, filtered like no noise happened! :D

PS: No need to swear at those unpractical dsp writers :D Writers whom I read for were practical I believe:

[1] Louis Litwin, "Matched filtering and timing recovery in digital receivers", rfdesign.com, September 2001

[2] Eric Jacobsen, http://www.dsprelated.com/showarticle/60.php

These were really useful.

Thank you for assisting me during this project KAZ :) Now I'm moving to carrier and symbol recovery, wish me luck.

Cheers

Thanks KAZ for assisting me throughout this project :)

First, I filtered the signal without noise... the output is pretty much the same as the input (in Matlab ) that's why I thought I might need to implement the matched filter in a different way. Later, I realized after many readings that matched filtering is useful in case of a polluted signal with AWGN. I added the noise and I could notice the difference!

No need to swear at those unpractical dsp writers :P Writers whom I read for are practical I believe:

[1] Louis Litwin, "Matched filtering and timing recovery in digital receivers", rfdesign.com, September 2001

[2] Eric Jacobsen, "Pulse Shaping in Single-Carrier Communication Systems"

Now I have a question, when I simulated in ModelSim, the demodulator is arranged as follows:

1) Mixer

2) then signal is passed to CIC decimation filter to remove high component frequency and to relax subsequent signal processings.

3) after that, I pass to RRC.

CIC is clocked at 100 MHz, RRC is clocked at 50 MHz (just like modulator if you remember)

I noticed that RRC's output is decimated by 2! It should produce a 2.8571 MSPS signal, instead it produces a 1.4285 MSPS.

I clocked it at 100 MHz, the output is 2.8571 MSPS again.

Question is, why is that? Although 2.8571 MHz is less than 50 MHz.

I was hopeful your radio will soon work and we will listen to Fahad Ballan music...

I really can't follow your problem of RRC decimation.

if it is single rate rrc filter the output speed should be same as input speed and none of your small figures.

It will help to give figures for sampling rate throughout your rx chain as clock rate is just an implementation issue.

OMG! You know Fahad Ballan!! Are you Syrian or Iraqi?

Back to RRC issue... I figured it out.

Take a look at this.. the input valid or sink valid signal of the RRC FIR is not coherent with the clock (clk)

https://www.alteraforum.com/forum/attachment.php?attachmentid=10345

I fixed it with this synchronizer circuit

https://www.alteraforum.com/forum/attachment.php?attachmentid=10346

and I got this

https://www.alteraforum.com/forum/attachment.php?attachmentid=10347

yes Iraq > 3 decades ago... my favorite was Delal shamali, Fahad Ballan and the comedian Ghawar Altosha

I looked at your waveforms and I see multiple clocks. I don't usually use more than 1 clock unless desperate.

Ohhh yeaaaah! Old days! How about Sa'doun Jaber, Elias Kheder and Kathem Alsaher? I really like them

I think I'm desperate here :D clk_dat (this is not really a clock, it's a counter) to drive serial to parallel block, clk_100 to drive CIC and NCO, clk to drive RRC.