Forum Discussion
Honored ContributorRouting HPS I2C thru FPGA Not Working
Hi
I followed Altera's guide AN706 (link below) to route HPS' I2C0 port through the FPGA on the Cyclone V Arrow SoCKit. I included the ALT_IOBUFF buffer as instructed by AN706 guide. But it's not working properly. We can send out I2C commands and we can see slave device sending ACK signal through an I2C analyzer. For some reason, the ACK is not reaching the HPS as we keep getting NACK from our code. We are using Quartus 13.1 while AN706 mentions Quartus 14.0. Not sure if that's the issue. Has anyone successfully routed the HPS I2C port through the FPGA and got it working? Any suggestions/help would be appreciated. www.altera.com/literature/an/an706.pdf14 Replies
Altera_Forum--- Quote Start --- I have played around with the sda hold time but no success... it looks like the sda signal gets out of the hps but not in again. (I can see the sda output and the ack from the slave but the controller says there was no ack) https://www.alteraforum.com/forum/attachment.php?attachmentid=12224 --- Quote End --- Hello nd89, how do you measure the signals? Thanks- Altera_Forum
I measured them with the signaltap and an oscilloscope... why?
- Altera_Forum--- Quote Start --- I measured them with the signaltap and an oscilloscope... why? --- Quote End --- When i try to measure with a signal tap, i cant see anything. It won't even trigger...
Marco_IntelNew Contributor
Hopefully you already solved this issue, but anyway some suggestions:
1- You need to enable internal timing arc from HPS to FPGA if you route the EMAC to FPGA I/Os, this is stated also in the CV HPS Handbook (vol 4 : Hps technical reference) where you can see that you need to add the following line into the HPS:
set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING ON
on Old version of Quartus you did need to enable those through an .ini file as you can find on the examples on rocketboards:
https://rocketboards.org/foswiki/view/Projects/CycloneVSGMIIExampleDesign
https://rocketboards.org/foswiki/Projects/CycloneVRGMIIExampleDesign
2- Seen that you're routing those signal through the FPGA you need to provide timing constraint to the I/O as usual (as if you're using an SGMII/RGMII interface depending on what you're using).
Hope it helps.
