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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Routing HPS I2C thru FPGA Not Working

Hi I followed Altera's guide AN706 (link below) to route HPS' I2C0 port through the FPGA on the Cyclone V Arrow SoCKit. I included the ALT_IOBUFF buffer as instructed by AN706 guide. But it's n...
Marco_Intel's avatar
Marco_Intel
Icon for New Contributor rankNew Contributor
6 years ago

Hopefully you already solved this issue, but anyway some suggestions:

1- You need to enable internal timing arc from HPS to FPGA if you route the EMAC to FPGA I/Os, this is stated also in the CV HPS Handbook (vol 4 : Hps technical reference) where you can see that you need to add the following line into the HPS:

set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING ON

on Old version of Quartus you did need to enable those through an .ini file as you can find on the examples on rocketboards:

https://rocketboards.org/foswiki/view/Projects/CycloneVSGMIIExampleDesign

https://rocketboards.org/foswiki/Projects/CycloneVRGMIIExampleDesign

2- Seen that you're routing those signal through the FPGA you need to provide timing constraint to the I/O as usual (as if you're using an SGMII/RGMII interface depending on what you're using).

Hope it helps.