New Contributor
Super ContributorHi Joseph,
May I know if there is any other warning/report why is the failing?
I also want to ask what kind of coding style might lead to routing congestion?
- Coding style here referred to recommended design practice for Intel FPGA device and Quartus e.g. how you inferred ram,dsp,multiplier etc. Since you are using hyperflex device (S10 and Agilex), they have a different kind of architecture thus different optimization e.g clocking, combi rtl, pipelining etc. Assuming this is a general congestion, you can visualize in congestion report in Compilation Report > Fitter > Route Stage > Global Route. Once you identify where is the congestion are, you can locate in chip planner to further debug, might be due to high fanout, thus you can do so register duplication to reduce the them etc.
Another way according to the document are as below:
https://www.intel.com/content/www/us/en/docs/programmable/683641/21-4/faq.html
1. 4.2.3.6. Guideline: Remove Fitter Constraints
2. 4.2.3.12. Guideline: Reduce Global Signal Congestion
3. 4.2.4.3. Guideline: Increase Router Effort Multiplier
4. 4.2.4.4. Guideline: Remove Fitter Constraints
5. 5.6. Periphery to Core Register Placement and Routing Optimization
You may refer more to below document I attach. I suggest you to refer to Design Recommendations as it will help you with the right technique to optimize the design.
