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Altera_Forum
Honored Contributor
Honored ContributorROM contents confusion
Hai, I have vhdl code for store a constant in ROM. The ROM is divided into odd and even; ROMO and ROME as shown below:
library IEEE; use IEEE.STD_LOGIC_1164.all; -- use ieee.STD_LOGI...
Altera_ForumHonored Contributor
Honored ContributorHow are those ROMs instantiated in the higher level component? If you want to write back a table with the input => output assignments in each ROM, you just need to read the data values in the order they are listed (and remember that (others => '0') means a data vector with all zeros). For example for ROMO:
addr data 000000 0 000001 GP 000010 FP 000011 FP+GP 000100 EP 000101 EP+GP 000110 EP+FP 000111 EP+FP+GP 001000 DP 001001 DP+GP 001010 DP+FP 001011 DP+FP+GP 001100 DP+EP 001101 DP+EP+GP 001110 DP+EP+FP 001111 DP+EP+FP+GP 010000 0 010001 FM 010010 DM etc... That said, I think you could replace those ROMs by the actual arithmetic operations they are supposed to accelerate. The synthesizer should be smart enough to optimize this and I'm not sure that using a ROM block for that is actually a good optimization.
