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_DMW_'s avatar
_DMW_
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2 years ago

Rise Time / Clock buffer impact on Stratix 2

Hello, I'm looking to change an oscillator that inputs into a stratix2 fpga. One of the constraints is not changing the firmware. The clock signal gets fed directly into on of the global clock b...
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TingJiangT_Intel's avatar
TingJiangT_Intel
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2 years ago

In fact, we barely pay attention to the rising time when designing,The signal recognition inside the device is also based on the level. As long as the level reaches Vh, the signal is considered to have reached a high level, and generally not too much attention is paid to the time it takes to rise.