Ring oscillator output always high

Hi Agentgates,

Honestly i have never tried to build such a design in FPGA before.

I could think of 2 concerns:

1) I am not sure if your the Quartus software could synthesis the pins properly. as there are no clk and reset or inputs. You can check compilation to see if the rtl was synthesis or if there are any part of the logic being ignored.

2) The other thing you could do is to build a simple logic either pushbutton to toggle or simple logic to drive high or drive low to see if the output pin are working. just to confirm the pin are working.