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DNewm1's avatar
DNewm1
Icon for New Contributor rankNew Contributor
5 years ago

RGMII support was removed from Cyclone 10 GX because the IP could not close timing. Can Intel share any more details of how the timing failures occur/the nature of the failures? Were they silent failures or did timequest show them?

RGMII isn't supported in the transceiver IP for C10GX. If a user wants to implement their own version in the LVDS IO running at a really low rate (around 125Mbps) is their any reason they can't? Were the timing failures in the IP blatant? Or were they silent failures?

1 Reply

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,

    The RGMII was not supported is because there is no way to meet timing. You are supposed to see the timing violation from the timequest if you have constraint design properly.

    For the LVDS IP implementation, you can refer to the TSE IP, it did support the LVDS I/O interface when you select the 10/100/1000Mb Ethernet MAC with PCS Core variant.

    Regards -SK