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Altera_Forum
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11 years ago

RGMII RX Clock on a non-clock pin (normal pin)

Hi there, I have some timing problems with my rgmii rx interface. Due to a design error the rx clock is not connect to an dedicated clock pin. This error results a high delay on clock path and ...
Altera_Forum's avatar
Altera_Forum
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11 years ago

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Hi there,

Is there anyway to compensate the error aftwards? (through an IP-Core or an assignment maybe?)

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Hi,

I think this is not recommended way to implement it, but in principle You could try to use logic resources for the clock routing towards the DDRIO-cell. In this case it could be the shortest path, and quite well matched with data..

e.g.

set_instance_assignment -name GLOBAL_SIGNAL OFF -to rx_clk

Then you should instantiate clkctrl -block to provide optimal clock for the rest of the domain.. Small design could work without clkctrl (at least design with only Altera TSE did meet timings without clkctrl). A bigger design that I tried failed without clkctrl,..

With Best Regards,

Jarkko

PS. This same feature can be found from Cyclone V GT FPGA Development Kit schematics :)