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I use a Arria V fpga. The plls are only reachable from clock pins. With any other pin the fitter complains with an error....
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Ok, I commented it might not be easy.
Does your FPGA have a clock input that is in common with your RGMII interface? If so, then you could use that for the PLL source, rather than the RX clock, and then you'd have to figure out the correct alignment to get things to work.
The best solution would be to try and wire the RX clock to a clock pin ... easier said than done on a multi-layer board ... but if your BGA balls have exposed vias, it would not be too impossible to solder a wire to both the PHY and FPGA ... but it might not be a particularly clean clock waveform.
Cheers,
Dave
Honored Contributor
