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Is there anyway to compensate the error aftwards? (through an IP-Core or an assignment maybe?)
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This is why you should place-and-route a design before the board is built :)
The two work-arounds I can think of are;
1. Add a rework wire to route the signal to a clock pin.
2. Use a PLL to phase-shift the clock so that you can meet timing.
Option (2) "sounds good", but since you have used a non-dedicated clock pin, you'll probably get warnings about that too. However, it might be enough for you to confirm that the RGMII interface works "well enough" so that you can move on and find any other hardware errors.
The long-term fix would require the board design be corrected, sorry.
Cheers,
Dave
Honored Contributor
