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Honored Contributor
Honored ContributorRestricted Fmax
Hello. I am using Quartus II v13sp1 WebEdition. Synthesis is performed for FPGA Cyclone II. As a result of simulation of any projects (both simple and complex) with the clock frequency g...
Altera_ForumHonored Contributor
Honored ContributorTHe cyclone 2 has 18bit x18bit embedded multipliers. So as long as each number is less than 18 bits, then the FMax of the multiplier wont change.
But if logic is required outside the multiplier, the higher the number of bits the lower the fmax.
