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Honored Contributor
Honored ContributorRestricted Fmax
Hello. I am using Quartus II v13sp1 WebEdition. Synthesis is performed for FPGA Cyclone II. As a result of simulation of any projects (both simple and complex) with the clock frequency g...
Altera_ForumHonored Contributor
Honored ContributorIt will take N clocks - where N is the length of the pipeline. Searching through rediculous high FMax is not going to factor in here - you should already know the clock you have.
Why do you need to know how long it will take? latency shouldnt be an issue - throughput is more important.
