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Altera_Forum
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10 years ago

Restricted Fmax

Hello. I am using Quartus II v13sp1 WebEdition. Synthesis is performed for FPGA Cyclone II. As a result of simulation of any projects (both simple and complex) with the clock frequency g...
Altera_Forum's avatar
Altera_Forum
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10 years ago

My project is a pipeline scheme - the multiplication of two n-bit numbers. The scheme consists of n-bit registers A and B of the multiplicand and the multiplier, a group of n elements AND, and vertical adder SM.

I need to know how long it takes from the receipt of the input data into the input registers scheme to get full results at the output. How do I estimate this interval using Quartus?