Forum Discussion
Altera_Forum
Honored Contributor
10 years agoRestricted Fmax
Hello. I am using Quartus II v13sp1 WebEdition. Synthesis is performed for FPGA Cyclone II. As a result of simulation of any projects (both simple and complex) with the clock frequency g...
Altera_Forum
Honored Contributor
10 years agoLet's look at the problem, about which I wrote earlier on a very simple example - an 8-bit counter lpm_counter.
Using Quartus 13.0sp1 Web Edition. Device Cyclone II EP2C35F672C6. Fmax = 518.4 MHz Restricted Fmax = 420.17 MHz Clock constraint assigned in value of 420 MHz. 1. Perform functional simulation project using the ModelSim Altera Starter Edition, clock - 420 MHz http://www.alteraforum.com/forum/attachment.php?attachmentid=11622&stc=1 We get the normal simulation results. 2. Perform timing simulation project using the ModelSim Altera Starter Edition, clock - 420 MHz http://www.alteraforum.com/forum/attachment.php?attachmentid=11623&stc=1 We get zero values on the outputs of the counter. 3. However, if you run the simulation time when clock = 420 MHz is not in ModelSim, and Quartus II Simulator - get the normal output value of the counter: http://www.alteraforum.com/forum/attachment.php?attachmentid=11624&stc=1 4. ModelSim Altera Starter Edition shows a non-zero values at the outputs of the counter only if the clock frequency reduced to 320 MHz or less: http://www.alteraforum.com/forum/attachment.php?attachmentid=11625&stc=1 How to Decide this problem with ModelSim simulation at a frequency of at most 320 MHz? Thanks