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Honored Contributor
Honored ContributorRestricted Fmax
Hello. I am using Quartus II v13sp1 WebEdition. Synthesis is performed for FPGA Cyclone II. As a result of simulation of any projects (both simple and complex) with the clock frequency g...
Altera_ForumHonored Contributor
Honored ContributorAnother quiz show ...
It is difficult to say more from your post. If timequest analysis perfomed right and it was reported such high Fmax properly and gate-level simualtion perfomed in different tools and you are expecting the same result from both tools then ask : where is right model? Did I get your question? If not, please make it clear.
