Forum Discussion
Altera_Forum
Honored Contributor
9 years ago --- Quote Start --- data_in : IN std_logic_vector(11 downto 0); ( including the signed bit ) -- converting to 31 bit signal l_data_in : signed(30 downto 0); l_data_in <= resize(signed(data_in),31); I was using the same thing that you posted, but all my converted values were 0 when I checked in signaltap --- Quote End --- I can assume your problem of zeros is not related to resize function failure. resize is simple function that extends the sign bit.