Forum Discussion
Altera_Forum
Honored Contributor
9 years ago --- Quote Start --- you didn't show your code. if it is std_logic_vector you need to define if it is resized as signed or unsigned so that negative values are filled with ones. data_resized <= resize(signed(data),18); -- assuming data is 16 bits std_logic_vector --- Quote End --- data_in : IN std_logic_vector(11 downto 0); ( including the signed bit ) -- converting to 31 bit signal l_data_in : signed(30 downto 0); l_data_in <= resize(signed(data_in),31); I was using the same thing that you posted, but all my converted values were 0 when I checked in signaltap