Honored Contributor
Honored ContributorI'd like to add some comments based on my ASIC design experience. One of the golden rules for ASIC design is OCPM (one clock per module). Sure, it's not possible to comply with a unknown rule. If you knew it and followed it then the question would not have arisen.
In the ASIC world (and in the FPGA world, too) there is a need to have one reset signal per clock domain and this usually is a fully synchronous reset, meaning that the signal is asserted and de-asserted synchronously. An asynchronous assertion is only needed in these seldom cases when the power-up level of output pins is critical for the external components of the system. Synchronour de-assertion is mandatory. One of your questions has not been answered fo far in this thread: What all are Altera recommended methods for synchronization when control signals move from a faster clock domain to a slower clock domain? I don't know what Altera recommends. But there is a simple answer: If a signal passes a clock boundary then it must be synchronized with the usual 2-flipflop stage. There is no exception. Cheers, Harald
